This application claims the benefit of Application No. 3938/2000, filed in Korea on Jan. 27, 2000, which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and in particular to a method for fabricating a semiconductor capacitor having a lower electrode with an increased effective surface area.
2. Description of the Background Art
Competition within the semiconductor industry has led to improved performance and decreased manufacturing costs. Manufacturers are able to decrease semiconductor costs by decreasing the size of the components installed on the semiconductors, thereby allowing the installation of more components on each semiconductor device. In the case of dynamic random access memory (DRAM) semiconductor devices, manufacturers are constantly working to improve the degree of integration among the components to further reduce fabrication costs. In a conventional DRAM semiconductor device, the size of the capacitor and transistor must be decreased to lower manufacturing costs. Methods of decreasing the size of the transistor are known. However, manufacturers have been unable to effectively reduce the size of the capacitor. For these reasons, further significant improvements in the manufacturability of DRAM semiconductor device require a reduction in size of the capacitor.
Various attempts have been made to reduce the size of the capacitor. For example, capacitor electrodes have been formed in a variety of geometric shapes in an attempt to increase the size of the electrodes, including the trench-type and stacked capacitors. Manufacturers have also attempted to use dielectric substance having high dielectric constants.
FIGS. 1A-1E show an example of sequential steps during the manufacture of a conventional DRAM semiconductor device.
As shown in FIG. 1A, a gate oxide film 101 and a gate electrode 102 are formed on a semiconductor substrate 100. A source 103 and a drain 104 are formed on opposite sides of the gate oxide film 101 and electrode 102 by implanting impurity ions into the substrate 100. The gate oxide film 101, the electrode 102, the source 103, and the drain 104 form a MOS transistor 120.
Referring to FIG. 1B, an interlayer insulating film 105 is formed on an entire upper surface of the semiconductor substrate 100, including the MOS transistor 120. A contact hole 106 is formed by etching the insulating film 105 over the source 103.
A polysilicon plug 107 is formed within the contact hole 106, as illustrated in FIG. 1C. A polysilicon film is formed on the polysilicon plug 107. The polysilicon film is patterned to form a polysilicon film pattern 108. The film pattern 108 has the same electrical connection properties as the polysilicon plug 107. The polysilicon film pattern 108 is a lower electrode of a capacitor of the DRAM semiconductor device.
As shown in FIG. 1D, a hemispherical silicon grain (HSG) film 109 is formed on a surface of the polysilicon film pattern 108. The HSG film 109 increases the effective surface area of the lower electrode of the capacitor.
A dielectric film 110 is formed on a surface of the HSG film 109, as seen in FIG. 1E. An upper electrode 111 of the capacitor is then formed on the dielectric film 110. The upper electrode 111 can be made of a metal or a polysilicon film.
This method of fabricating a conventional semiconductor includes a number of disadvantages. The capacitor formed by this process is a metal-insulator-semiconductor (MIS) type capacitor having a polysilicon lower electrode and a metal upper electrode. An MIS capacitor produces an asymmetric voltage-capacitance (C-V) curve, resulting in a deterioration of the characteristics of the capacitor. Further, the step of forming the HSG film to increase the effective surface area of the lower electrode complicates the manufacturing process, since a silicon seed film must be formed on the surface of the lower electrode, and the seeded electrode must be annealed under considerably controlled conditions. It is also difficult to produce HSG films having a constant thickness. For these reasons, it is difficult to manufacture a capacitor by this conventional method having a desired capacitance.
Accordingly, the present invention discloses a method of fabricating a semiconductor capacitor having a symmetric C-V curve by providing a capacitor with a metal-insulator-metal (MIM) structure wherein both the upper and the lower electrodes of the capacitor are formed of metal.
The present invention also discloses a method of fabricating a semiconductor capacitor having a lower electrode with an increased effective surface, without using a complex HSG film formation step.
The present invention provides a method of fabricating a semiconductor capacitor including forming an impurity layer on a semiconductor substrate. An interlayer insulating film is formed on the impurity layer. A contact hole is formed on the impurity layer by selectively etching the interlayer insulating film. A conductive plug is formed in the contact hole. A metal film pattern is formed on the conductive plug. An irregularity is formed on the surface of the metal film pattern. A dielectric film is formed on the surface of the metal film pattern. A metal film or electrode is formed on the dielectric film.
Forming the irregularity on the surface of the metal film pattern can include forming a polysilicon layer on the surface of the metal film pattern. A silicide layer can be formed by a silicide reaction at an interface between the polysilicon layer and the metal film pattern. The polysilicon layer and the silicide layer can be removed.
The present invention further provides the method of fabricating the semiconductor capacitor wherein a material of the metal film pattern includes W, and the formation of the silicide layer includes annealing at a temperature of between about 600xc2x0 C. and about 1300xc2x0 C.
The present invention further provides the method of fabricating the semiconductor capacitor that includes annealing the metal film pattern in at least one of an N2 plasma, an NH3 plasma, an N2 atmosphere, and an NH3 atmosphere, after removal of the silicide layer.
The present invention further provides the method of fabricating the semiconductor capacitor wherein a material of the metal film pattern includes Pt, and the formation of the silicide layer includes annealing at a temperature of between about 400xc2x0 C. and about 1000xc2x0 C.
The present invention further provides the method of fabricating the semiconductor capacitor wherein a material of the metal film pattern includes Ti, and the formation of the silicide layer includes annealing at a temperature of between about 500xc2x0 C. and about 1100xc2x0 C.
The present invention further provides a method of fabricating a semiconductor capacitor having a substrate and an impurity layer on the substrate. A conductive plug is formed in contact with the impurity layer. A metal film pattern having an irregular surface is formed on the conductive plug. A dielectric substance film is formed on the metal film pattern.
The present invention further provides a semiconductor capacitor. A semiconductor substrate includes an impurity layer. A conductive plug contacts the impurity layer. A metal film pattern is disposed on the conductive plug. A dielectric substance film is installed on the metal film pattern.